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Author: Admin | 2025-04-28
In the testbench a clock of 10ns is specified and the input 'in'is connected to a constant 1. We use the program Cadence SimVision to look atthe waveform database that was created by Verilog-XL. Type the followingcommand: simvisionNow we need to open the Waveform database. Click on the "Open"symbol, choose the directory "shm.db",which is where the file is located, and double-click on the file "shm.trn" to open it. To see the contents of thewaveform database, click on "stimulus": Nowwe want to plot our waveforms. We need to select which signals we areinterested in. In this case letslook at all waveforms. Select all 4 waveforms on the right and hit thepicture-button with the square waves. Wesee that the circuit works fine. At every rising clock edge the output changes.2.Logic Synthesis using Design CompilerOnce you have verified that your Verilog RTL code is working correctly youcan synthesize it into standard cells. The result will be a gate-level netlist that only contains interconnected standard cells. There are template files for all the following steps already prepared foryou. We will now copy those templates into our project. cp /import/scripts/FreePDK45_2011/FreePDK45/osu_soc/flow_ece429/* .(If you use the machines in the laboratory, you may find that this command does not work. This is because the target folder does not exist in the local machines in 310 laboratory. The command will work if you login to 'uranus' or 'saturn' server. In case you need to use them in 310, you can downlaod them from here: compile_dc.tcl , encounter.conf, encounter.tcl. Put
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